Existing low latency, high bandwidth, high capacity Dual Inline Memory Module (DIMM)-based Dynamic Random Access Memory (DRAM) systems have been optimized for the common case of deterministic, error-free operation. However, these systems lack a particularly efficient means of returning precise exception condition or status information back to the host system. The protocol overhead of status polling, combined with the deterministic latency optimizations results in the excessive consumption of memory channel resources. Furthermore, obtaining status information using interrupt-based signals require multiple transactions with complex flow control.
As DIMM-based memory systems evolve to encompass heterogeneous memory types (i.e., DRAM and Flash hybrid DIMMs) and greater local control of per-DIMM resources are implemented, an increased amount of status information may need to be communicated back to the host. Therefore, a low-overhead means of in-band status signaling using the existing protocols and infrastructure is desirable.